;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
;
;   Self calibrating TCXO controller
;
;   A minimalistic GPSDO for low performance self-calibrating systems
;   (then again, we may have differing definitions of 'low performance')
;
;
;
;
;   (C) 2010 Kasper Kjeld Pedersen
;   ----------------------------------------------------------------------------
;   "THE BEER-WARE LICENSE" (Revision 42):
;   Kasper Kjeld Pedersen wrote this file. As long as you retain this notice you
;   can do whatever you want with this stuff. If we meet some day, and you think
;   this stuff is worth it, you can buy me a beer in return
;   ----------------------------------------------------------------------------
;
;
;   Please note that this design has limited range - 2 ppm or so.
;   If the oscillator is outside of this range, the PPS will be considered
;   invalid, and it will coast on the eeprom-stored DAC values.
;
;   While PPS is good and being tracked, it will store the DAC value to eeprom
;   every 27 minutes.
;
;
;   Pinout (ATTiny13):
;
;                  _______
;               reset ^   vcc
;   10MHz -->   clock  serial  --------[1k]---> terminal
;   PPS----->   pps      bpwm  ---->lowpass filer---> vco-input
;               gnd______apwm  ---->lowpass filter---> error meter
;
;
;  bpwm is the loop output. Sigma-delta technique is used to give 16 bit resolution.
;  It should be passed through a filter that has a time constant of less than 10
;  seconds, and attenuates 39kHz by at least 39000 times.
;  22k 180uF as used in the prototype has tc=4 sec and attenuation=1M
;
;  apwm outputs the estimated frequency error. 0%-50%-100% is -50ppb - 0 - +50ppb
;  For connection to an analog panel meter. Will center until pps is received.
;  A 10ms+ filter is suitable - 50k 1uF would be good for driving a 100uA meter.
;
;  The PPS input is rising edge sensitive.
;  Minimum PPS low time is 5 us. Minimum PPS high time is 600ns.
;  The input does not need to be 1Hz. Any integer frequency up to 100kHz will
;  work. Provide an external 500k or less pullup or pulldown if it can be
;  left unconnected.
;
;
;  The serial output is a RS232 polarity (ie. idle 0V) 38400 bps, 8 data bit,
;  no parity, 1 stop bit. The output format is
;
;  <dacvalue> <space> <ppstime> <space><goodcount> <space><frqerr> <cr> <lf>
;  example string:
;  C259 02 FF FB
;  ++++             DAC: goes from 0000 to FF00. 
;       ++          PPS timing: Goes from -20 to +20. -20 would be sent at "EC"
;                   A value of 2 means that the PPS edge arrived 200ns 'late'.
;          ++       GoodCount: Set to 00 whenever PPS lock is lost. Then counts
;                   good pulses, and when 255 good ones are seen, the PLL starts
;                   using the information. 
;             ++    FrqErr: From -128 (0x80) to +127 (0x7F) in units of 4E-10.
;                   The estimated error of the vco based on a tau of 4 minutes.
;                   When positive, the vco is fast.
;                   
;
;
;
;  Calculating the resulting time constant:  
;  if the oscillator is 1ppm low, the loop will step the adc SPAN*10/65536 per second.
;  Thus, if the vcxo range is 1 ppm, the time constant is 6554 seconds.
;
;
;                               6553.6
;  time constant in seconds =  ------------------------------------------
;                               (vcxo change in ppm for 5V)  * more_gain
;
;  more_gain is a user programmable figure in the range 1..5.
;
;
;
;
;  My test TCXO setup v1:
;     gain of 5 on a 2ppm range gives 655 seconds tau.
;     the frequency step for 100ns (the PPS error) is thus 100ns/655s = 0.15 ppb = 1.5E-10
;     which is smaller than the freq-err readsout resolution.
;
;  My test TCXO setup v2:
;     gain of 1 on a 2ppm range gives 54 minute tau.
;     the frequency step for 100ns (the PPS error) is thus 100ns/655s = 0.15 ppb = 1.5E-10
;     which is smaller than the freq-err readsout resolution.
;
;
;




;;;;;;;;;;;;;;;;;;;;; SETTINGS ;;;;;;;;;;;;;;;;;;;

;this setting decreases the time constant.
#define MOREGAIN_1
;;#define MOREGAIN_2
;;#define MOREGAIN_3
;;#define MOREGAIN_4
;;#define MOREGAIN_5

;which way does the VCO swing? POS if a positive control voltage raises frequency
#define DFDV_NEG
;;#define DFDV_POS


;this will cause internal pullup on pps when no pps is present.
;Convenient, but can degrade pps-less accuracy slightly if
;the pps pin is also driven low.
;#define PPSAUTOPULL




;this define boosts the loop to 1kHz. without it simulation takes AGES.
;not for use in hardware unless you really know what you are doing.
;#define DEBUG1KHZ







.INCLUDE "TN13DEF.INC"

.def irqscratch=r1
.def timerM = r2
.def timerH = r3
.def nextL = r4
.def nextM = r5
.def nextH = r6
.def dacL = r7
.def dacH = r8
.def lasterror = r9
.def good_pps_counter = r10
.def deltasigmaacc = r11
.def irqwork = r12
.def frqavgH = r13
.def frqavgL = r14
.def storetimerL = r15
.def storetimerP = r16


v_reset:   rjmp start
v_int0:    nop
v_pcint:   rjmp target_of_pcint
v_ovf0:    rjmp ovf0_irq
;v_eerdy:   nop
;v_anac:    nop
;v_t0a:     nop
;v_t0b:     nop
;v_wdt:     nop
;v_adc:     nop


start:

#ifdef DFDV_POS
	ldi r24, (1<<COM0A1) | (1<<COM0B1) |(1<<WGM01)|(1<<WGM00)  ; for positive df/ft
#endif

#ifdef DFDV_NEG
	ldi r24, (1<<COM0A1) | (1<<COM0B0)|(1<<COM0B1) |(1<<WGM01)|(1<<WGM00)  ; for negative df/ft
#endif
	

	out TCCR0A,r24
	ldi r24, 1         ;10MHz pwm timer
	out TCCR0B,r24
	ldi r24,(1<<TOIE0)
	out TIMSK0,r24

	ldi r24, 1<<4
	out PCMSK,r24

;;;;;;;;;;;;;;;;;; read old value from eeprom ;;;;;;;;;;;;;;;;
    rcall read_ee
    ;check it for being FFFF
    mov r24,dacH
	and r24,dacL
	com r24
	brne good_ee  ;the one we found was FFFF
bad_ee:
	ldi r24,0x7F
	mov dacH,r24   ;approximate centering to speed up matters
good_ee:




	ldi r24, 7  ;bit 0,1,2, see the commented-out instructions for the meaning of each
	out DDRB,r24
    ;sbi DDRB,0 ;frequency error meter
	;sbi DDRB,1 ;vco voltage
	;sbi DDRB,2 ;serial data


	clr frqavgH ;center meter at power up to help adjustment
	ldi r24,0x80
	out OCR0A,r24

	clr storetimerL ;27 minutes to first write

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

acquire_pps:
#ifdef PPSAUTOPULL
    sbi PORTB,4 ;pullup on PPS
#endif
acquire_pps_retry:
	sei
	clr good_pps_counter ;also works as a nop to handle interrupt = timer overflow
	cli
    sbic PINB,4
    rjmp acquire_pps_retry
wait_for_act:
	in irqscratch,TIFR0            ;;timing calibration: breakpoint here, and toggle the pps bit
 	sbrc irqscratch,TOV0
	rjmp acquire_pps_retry
    sbis PINB,4
	rjmp wait_for_act
  	;we have an edge, 6 clock span

	in nextL,TCNT0
	mov nextM,timerM
	mov nextH,timerH

	in irqscratch,TIFR0
 	sbrc irqscratch,TOV0
  	rjmp acquire_pps_retry
    sei

	ldi r24,0x80 -127  ;add 10M clocks, minus the lead-in delay. There is 128 clocks latency in the tracker code, so compensate
	add nextL,r24
	ldi r24,0x96
  	adc nextM,r24
  	ldi r24,0x98
  	adc nextH,r24

#ifdef DEBUG1KHz
    rcall adjust_1kHz
#endif

 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

mainloop:
	ldi r24,0x80
	add r24,frqavgH
	out OCR0A,r24


;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; PPS tracker ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
retry_read_timer:
	sei
	nop ;eat interrupt
	cli
	in r24,TCNT0
	mov r30,timerM
	mov r31,timerH
	in r25,TIFR0
	sbrc r25,TOV0
	rjmp retry_read_timer     ;no pending overflow: we have a clock reading that is valid

	sub r24,nextL
	sbc r30,nextM
	sbc r31,nextH   
	cpi  r31,0      ;(now-set) mod 2**24 has become small
	brne retry_read_timer
  ; we are now after the setpoint. r24 has become positive, and shows how late we are
    ldi r30,80   ;;; <--- calibration constant, also maximum interrupt time allowed
	sub r30,r24 ;r30 is the number of clocks to wait
coarsedelay:     
	subi r30,3           ;result when carry: -3 -2 -1      11111101 11111110 11111111
	brcc coarsedelay
finedelay:
    sbrc r30,1           ;consumes 4 clocks when '2', 2 clocks when 0,1
	lpm                  ;z is small positive
    sbrc r30,0           ;consumes 2 clocks when '1', 1 clocks when 0 and 2
	adiw r30,0
;;;;;;;;;; we get here with an exact cycle delay relative to the setpoint
	ldi r24,1<<PCIE  ;; PCIE and PCIF are in the same bit position. enable it, and clear the flag.
	out GIFR,r24     ;PCIF  ; this sets up a hardware branch to the end of the increment list
	out GIMSK,r24    ;PCIE
    ldi r24,0
    out TIMSK0,r24 ;no automatic timer overflow handling
    sei
    clr r24     ;we cannot get an interrupt here, in the cycle after sei, so this is a good place to zero it

	inc r24 ;-2.0 microseconds
	inc r24
	inc r24
	inc r24

	inc r24
	inc r24
	inc r24
	inc r24
	inc r24
	inc r24
	inc r24
	inc r24

	inc r24
	inc r24
	inc r24
	inc r24 ;;timing calibration: breakpoint here, and toggle the pps bit
	inc r24
	inc r24
	inc r24
	inc r24 
             ;;;; capture field center
	inc r24
	inc r24
	inc r24
	inc r24
	inc r24
	inc r24
	inc r24
	inc r24

	inc r24
	inc r24
	inc r24
	inc r24
	inc r24
	inc r24
	inc r24
	inc r24

	inc r24
	inc r24
	inc r24
	inc r24 ; +2.0 microseconds
    
    cli	
    ldi r24,255 ;no capture
target_of_pcint_cleaned:
	ldi r30,0
	out GIMSK,r30      ;PCIE disable
	sei
	ldi r30,(1<<TOIE0)
	out TIMSK0,r30     ;reenable the overflow handler
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; compute next time
    
    sbrc r24,7
	rjmp acquire_pps

#ifdef PPSAUTOPULL
    cbi PORTB,4 ;turn off the pps. we are connected to an external source
#endif

    subi r24,20 ;center field.

	ldi r25,0x80  ;expected arrival at +10M
	add r25,r24   ;

	add nextL,r25
  	ldi r25,0x96
	adc nextM,r25
	ldi r25,0x98
  	adc nextH,r25 

#ifdef DEBUG1KHz
    rcall adjust_1kHz
#endif
;;;;;;;;;;;;;;;;;;;;;;;;;;; pps tracker ends here. r24 is the result ;;;;;;;;;;;;;;;;;;;;;;;;;;
    ;r24 is +1 if the pulse arrived 100ns late. Span is +/- 24

    ; If the VCXO span is 1ppm, and we adjust 1 dac step at 100ns error per second,
	;   the step size becomes 1 us/s /65536 = 0.015 ns/s (15E-12)
	;   and 100ns / 0.015 ns/s = 6666 seconds

	push r24
	inc good_pps_counter
	brne good_pps_counter_not_good
	dec good_pps_counter

	;;;;;;;;; we have 128 good pps pulses in a row ;;;;;;;;;
	;
	; The time information we use is the one old by 1 second.
	; This way, when the pps signal is disconnected, even if
	; it happens in the 4us window, we will not use bad pps.
    ; if the VCXO has positive df/dv, we need to subtract if the error is positive, because WE are fast
	;;;;;;; subtract lasterror from dac
	rcall complicated_loop
	    
	;;;;;;;; the actual adding must be done cli'd since it is also used from interrupt
	cli
    sbrc lasterror,7
	rjmp lasterror_negative
lasterror_positive:
    ldi r25,0x00
    sub dacL, lasterror
	sbc dacH,r25
    ;if we get a carry here, we underflowed. If we did not get a carry, we are good
	brcc lasterror_done
    rjmp lasterror_atlimit
lasterror_negative:   
    ldi r25,0xff
    sub dacL, lasterror
	sbc dacH,r25
	;if we did not get a carry, we overflowed. 0xFF80 - 0xFF81=FFFF+carry, ok
	brcs lasterror_done
lasterror_atlimit:
    mov dacL,r25    ;limit to 0000 and FFFF
	mov dacH,r25
lasterror_done:
	;;;;;;; the delta-sigma pwm will overflow if it attempts to add anything to FF
	mov	r24,dacH
	cpi r24,0xFF
	brne dac_not_pegged
	clr dacL
dac_not_pegged:
	sei
	;;;;; all done adding

	subi storetimerP, -40 ;  27 min interval.
	brcc not_storetime
	inc storetimerL
	brne not_storetime
    rcall store_ee              ;;destroys r24,r30,r31
not_storetime:

good_pps_counter_not_good:
	pop lasterror ;the error for THIS acquisition. was r24


    ;frequency error decay: tau=256 seconds. so a value of 128 (fullscale) means 50ns/s. 1 step is thus 4E-10
	clr r24
    sbrc frqavgH,7 ;sign extend
	dec r24        ;FF
	sub frqavgL, frqavgH
	sbc frqavgH,r24

	;frequency error averaging with saturation
	add frqavgH, lasterror
	brvc frqavg_no_ov
    ldi r24, 127
	sbrc lasterror,7
    ldi r24, -128
    mov frqavgH, r24
frqavg_no_ov:



;;;;;;;;;;;;;;;;;;;;;;;;;;;;; adjustment done. ;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;; dump data to serial interface.

	; irq rate is 39062. close enough to 38400 bps for us.
	;
    ; 4 digits DAC information, 2 digits error info, 2 digits good count
	; DDDD EE CC
	; 
	; 0000         minimum dac
	; 7FFF         center dac
	; FF00         maximum dac
	;      FF      we are running 100ns slow
	;      00      no time error
	;      01      we are running 100ns fast
	;         00   cannot acquire PPS lock. Too much offset
	;         FF   pulses are good. 
    ;            XX frequency error 

    mov r24,dacH
	rcall transmit_hex_byte
    mov r24,dacL
	rcall transmit_hex_byte
	rcall transmit_byte ;space

    mov r24,lasterror
	rcall transmit_hex_byte
	rcall transmit_byte ;space

    mov r24,good_pps_counter
	rcall transmit_hex_byte
	rcall transmit_byte ;space

    mov r24,frqavgH
	rcall transmit_hex_byte

	ldi r24,13
	rcall transmit_byte
	ldi r24,10
	rcall transmit_byte
    
    rjmp mainloop



complicated_loop:
    ;optional loop hacks go here.
	;here we may manipulate lasterror as desired.
	;if we accumulate the input, we get time offset.
	;if we add that I term to lasterror before returning, we can compensate for aging.
#ifdef MOREGAIN_5
    mov r24,lasterror
    add lasterror,lasterror ; 24->48
    add lasterror,lasterror ; 48->96
	add lasterror,r24 ; 96+24= 120
#endif
#ifdef MOREGAIN_4
    add lasterror,lasterror ; 24->48
    add lasterror,lasterror ; 48->96
#endif
#ifdef MOREGAIN_3
    mov r24,lasterror
    add lasterror,lasterror ; 24->48
	add lasterror,r24 ; 96+24= 120
#endif
#ifdef MOREGAIN_2
    add lasterror,lasterror ; 24->48
#endif

	ret

#ifdef DEBUG1KHz
adjust_1kHz:
	;ldi r24,0x70  ;subtract 10M-10000 clocks
	;sub nextL,r24
	;ldi r24,0x6F
  	;sbc nextM,r24
  	;ldi r24,0x98
  	;sbc nextH,r24
	ret
#endif






ovf0_irq:
	in irqscratch,SREG
	mov irqwork,dacH
    add deltasigmaacc,dacL
	brcc no_ds_cy
	inc irqwork
no_ds_cy:
	out OCR0B,irqwork
	inc timerM
	brne ovf0ret
	inc timerH
ovf0ret:
	out SREG,irqscratch
	reti


target_of_pcint:
    pop irqscratch ;;get rid of pushed program counter
	pop irqscratch
	rjmp target_of_pcint_cleaned




store_ee:
    ;compute write address
  	ldi r31,0x1F                  ;controller address
    rcall read_ee_byte
	com r24
	andi r24,0x10                 ;flip controller
	add r31,r24  ;0x20 or 0x30

    mov r24,dacL
	rcall store_ee_byte        
    mov r24,dacH
	rcall store_ee_byte
	mov r24,r31
  	ldi r31,0x1F
    ;rjmp store_ee_byte           ; controller flipin eeprom
	;fallthrough
store_ee_byte:
    sbic EECR,EEPE
	rjmp store_ee_byte
	ldi r30, 0
	out EECR, r30
    out EEARL,r31
	out EEDR,r24
	sbi EECR,EEMPE
	sbi EECR,EEPE
	inc r31
	ret


;scan for 2 identical copies of DAC setting.
read_ee:
    ;compute read address
  	ldi r31,0x1F                  ;controller address
    rcall read_ee_byte
	andi r24,0x10                 ;flip controller
	add r31,r24  ;0x20 or 0x30
	rcall read_ee_byte
	mov dacL,r24
	rcall read_ee_byte	    
	mov dacH,r24
	ret

read_ee_byte:
    sbic EECR,EEPE
	rjmp read_ee_byte
	out EEARL,r31
	sbi EECR,EERE
	in r24,EEDR
	inc r31
	ret






transmit_hex_byte:
	push r24
	swap r24
	rcall transmit_hex_digit
	pop r24
	;fallthrough
;;;;;;;;;;;;; hex transmit digit;;;;;;;;;;;;;;;;;;;;;;;;
transmit_hex_digit:
	andi r24,0x0F
	subi r24,-48
	cpi  r24,58
	brcs transmit_byte ;0..9
	subi r24,-7       ;65 - 48 -10= 7
	;fallthrough
;;;;;;;;;;;;; softuart transmit ;;;;;;;;;;;;;;;;;;;
transmit_byte:        
	rcall wait_bit
	sbi PORTB,2 
	ldi r25,9
bitloop:
	rcall wait_bit
	sbrs r24,0
	sbi PORTB,2
	sbrc r24,0
	cbi PORTB,2
	sec         ;stopbit. after 8 iterations the register is all-1
	ror r24
	dec r25
	brne bitloop
	ldi r24,32      ;this makes inserting spaces cheaper
	;;ret           ;r24=32,r25=0 on return
	;fallthrough. Saves a word, and adds an additional stop bit (8N2), fine for 8N1 receivers.
wait_bit:
	mov r0, timerM
wait_internal:
	cp r0,timerM
	breq wait_internal
	ret